In computer systems, information is stored on magnetic storage systems such as Winchester type hard disks or floppy disks. Data is stored in a series of spiral or concentric rings known as "tracks". The data consists of transitions of polarity of magnetic particles on the disk surface. A number of schemes are used to detect these transitions and data.
One prior art, data detection method is a peak detection system. A disadvantage of peak detection scheme's is limited to data density. Another prior art scheme, as known as partial response class IV (PR-IV) signaling. Systems using these PR-IV schemes can achieve higher density recording than conventional peak detection systems.
A PRML (partial-response maximum likelihood) channel can be used to achieve high data density in writing and reading digital data of pulses on the disks.
PRML coding assumes a lineal channel. However, the recording characteristics of the magnetic medium such as a disk are non-linear due to non-linear magnetic effects such as, partial erasure.
Non-linear distortion in the channel and consequently in the recording process on the magnetic medium leads to degradation at higher density and data rates. Narrow pulses in certain patterns digital data signals experience pulse compression and other non-linear pulse-edge displacement effects when stored magnetically on a disk file. This results in pattern dependent, edge shifts of the transition. The resulting data when read back from the disk has a higher error rate because of non-linear edge timing shifts of the pulses which reduce the timing margin for error of the data detection system. If the pattern-dependent edge shifts of the pulses can be ascertained for a particular medium, then it is possible to preshift the data write pulses edges by the amount equal and opposite to the direction which the medium will shift them to eliminate the pattern dependent, edge shifts. As a result, data is written on the magnetic medium with a correct timing relationship read back from the disk. Timing precompensation solves the problem of pattern dependent, edge shifts and decreases error rates when the data is read back for accuracy and increases the disk file capability. Particular algorithms for determining which pulse edge to shift are well known and not described in detail. The amount of capacity improvement attainable for any algorithm depends on the accuracy of the time shifts delivered by the precompensation circuit.
User files are stored along these concentric tracks defined in magneticable surface coding on the surface of the rotating disk. To this end, during storage of the user file, user data is encoded and bits of encoded file are serially clock to the write head driver that passes an electronic current through a write head which is adjacent to a selected disk surface to magnetize segments of the select data track in a pattern that reflects the sequence of logical values of bits that include the encoded user file. These magnetized segments, in turn, produce a magnetic field that can be sensed by read head during reading to generate a sequence of electrical pulses that reflects the pattern of magnetization of the data track to prevent the recovery of the encoded file for decoding and one returned to the computer which makes use of the hard disk drive for another user file.
As described, write precompensation is a technique associated with the minimization or removal of the effects of non-linear transitional shift (NLTS) that can occur in high density magnetic recording. Non-linear transition shift is a write effect caused by magneto-static interactions that occur between closely spaced magnetic transitions. When adjacent magnetic transitions are recorded close together, NLTS causes a transition that immediately follows a preceding transition to be shifted or drawn towards the preceding transition such that the spacing is altered from the ideal. When incorrect NLTS causes degradation of overall recording performance.
As magnetic recording densities become greater and greater, write precompensation techniques have become increasingly important to compensation for the detrimental effects of NLTS. Write precompensation involves delays in time at which adjacently recorded transitions are written into a magnetic medium so that adjacent transitions are recorded where intended, for example in proper bit spacing on the medium relative to the write clocking signal. A write precompensation "looks" at user data stream as it is written to the disk and detects the situation where two or more situations are transitions immediately follow each other without sufficient intervening bit times. The write precompensation circuit is able to adjust the relative delay (or phase with respective to the write clock) of the transition following a preceding transition in order to carry out the necessary precompensation relative to the write clock signal.
Application of precompensation delay causes the effected transitions to be time delayed by the appropriate amount, often expressed as a percentage of nominal bit cell period or a percentage of delay established by the write clock signal. With the emergence of PRML systems in magnetic systems, non-linear transition shift and write compensation has become of a particular concern.
A problem with previous precompensation write circuits is that the amount of time that the affected transition is delayed is insufficient.
Typically, the data to be written and the corresponding transitions to be written are synchronized to a time based generator (TBG) in the recording channel. This clock is used to write data onto the recording medium.
As described above, precompensation is accomplished by altering the actual position of the data transitions that are recorded onto the storage medium. In order to accomplish precompensation, a plurality of clock phases are used to alter the actual positions of the data transitions. Typically, a ring oscillator including a voltage controlled oscillator is employed. With a ring oscillator VCO, multiple phases are available for output by using the output of different delay stages in the ring oscillator. However, a problem with the ring oscillator is the number of stages used in the ring oscillator. The number of phases is limited to twice the number of stages in the ring oscillator. For example, if the ring oscillator has ten stages, then there is only 20 phases that are obtainable from the output. Consequently, the resolution is limited to 5% (resolution=1/2.times. number of stages in the ring oscillator). FIG. 1 illustrates a ten stage ring oscillator connected to a ten-to-two phase multiplexer with a precompensation phase select. The output of the ten-to-two phase multiplexer is output to a two X phase interpolation circuit. This system described in FIG. 1 operates satisfactory if the data rate of operation is not too high. As the data rate increases, problems result with the ten stage ring oscillator in terms of power dissipation. For 325 Mbps, operation, the ten stage ring oscillator will be running at 345.5 Mhz. This requires a large amount of power. The frequency linearity and the gain of the VCO will be a problem at this high data rate. This causes a speed bottle neck in the phase lock loop (PLL) which is typically used in a channel.
Additionally, frequency linearity will suffer because each delay stage in the ring oscillator has a fixed gate delay T.sub.fixed and a variable delay T.sub.ADJ depending on the V.sub.ADJ control voltage from the PLL filter. The total delay from a single delay stage is illustrated in Equation 1. EQU T.sub.fixed +T.sub.adj =T.sub.delay Equation 1
For each clock cycle, the signal is required to go through all the delay stages twice. Thus, the clock period of the oscillator output T.sub.vco is illustrated in Equation 2. EQU T.sub.vco =20T.sub.delay =20(T.sub.fixed +T.sub.adj)-20T.sub.adj +T.sub.Constant Equation 2
where T.sub.Constant =20T.sub.fixed.
Ideally, the oscillator should be linear. More specifically, the relationship between the control voltage V.sub.adj and the oscillation frequency should be linear. To achieve this linearity, T.sub.vco should depend only on V.sub.adj. Consequently, T.sub.Constant should be relatively small (and as small as possible) as compared to the 20 T.sub.adj. At a low data rate (frequency), these constraints are satisfied, and the system operation is satisfactory. However, as the data rates increases, these assumptions are no longer valid and the system starts to demonstrate non-linearity relationships when T.sub.Constant approaches that of T.sub.ADJ. As a result, the frequency linearity and the gain of the VCO will suffer. Thus, a design goal is to reduce the constant delay term T.sub.Constant. Typically, the most straightforward ways achieve this result is to use less delay stages or to reduce T.sub.fixed of the delay stages as illustrated in Equation 3. EQU T.sub.Constant -2n.times.T.sub.fixed Equation 3
where n is the number of stages in the ring oscillator.
FIG. 2 illustrates the phase diagram of a 10 stage ring oscillator. The arrows 1200 illustrate the equally distant phase output of the ring oscillator.
This case no phase interpolation is employed, the precompensation resolution P.sub.res is only 5% since P.sub.res is defined as Equation 4. EQU P.sub.res =(1/2n).times.100% Equation 4
This provides insufficient precompensation for high data rates. Typically, at the very least, the precompensation resolution should be below 3%. As illustrated in FIG. 3, a 2X phase interpolation provides a resolution of 2.5% . FIG. 3 illustrates element 1300 being the phase output from the 10 stage ring oscillator while element 1302 illustrates the additional phases obtained from the 2X interpolation. As illustrated by FIG. 3, if fewer delay stages are employed, the resolution of pre-compensation will be increased. As discussed, this is too coarse for high rates.
FIG. 4 illustrates a 2X phase interpolation circuit. Each phase, namely phase A and phase B, are input to a ramp generator. This phase causes a ramp signal to be generated which are summed by a summation circuit. The results are threshold compared and the edge corresponding to the zero crossing point is output to the write precompensation clock. Typically, the 2X interpolator circuit generates two ramps by two ramp generators namely, ramp A and ramp B from two adjacent phases. The phases are phase A and phase B output from the ring oscillator. Additionally, these two ramp generators have identical gain and slew rate. The output from the ramp generators are illustrated in FIG. 5. The two ramps are summed and the summed result is illustrated as trace 2 (solid line). If only one single phase (either phase A or phase B) is input to the phase interpreter, as illustrated as trace 1 (ramp A+ramp A) or trace 3 (ramp B+ramp B) will be produced. The zero-crossing points of these three traces, as illustrated in FIG. 5 are separated from each other by 1/2 the phase difference between phase A and phase B with respect to trace 2 and the middle between trace 1 and trace 3. Thus, the zero-crossing points from the summation of the ramps provide the desired phase interpretation locations. The zero-crossing points are converted by a differential comparator (CMP) to a specific clock phase that can be used by precompensation circuit to write the data. However, this circuit suffers from the disadvantages described above namely, large power usage, unsuitability with high data rates and insufficient resolutions.